The present invention relates to a semiconductor memory device incorporating fuse-cells in which data for setting a mode corresponding to a plurality of types of products and redundancy data or the like for use in a redundancy technique is stored.
A semiconductor memory device arranged to cause data for setting a mode corresponding of a plurality of types, for example, data for changing the number of bits of an I/O, to be stored in a nonvolatile memory cells so that change in the number of bits of the I/O is permitted has been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2-116084, Jpn. Pat. Appln. KOKAI Publication No. 2-243677 and so forth.
Recently also redundancy data for use in an operation for substituting a spare column/row for a defective column/row, that is, in a so-called redundancy technique is stored in a nonvolatile memory cells in place of the fuse. The foregoing technique has been put into practical use. In this specification, the nonvolatile memory cell in which data for setting a mode and redundancy data is stored is called a "fuse-cell".
Data stored in the fuse-cell is data for determining the type of a product and data for changing a defective column/row into a spare column/row. The above-mentioned data must be read/latched before an apparatus is usually operated. Therefore, a semiconductor memory device incorporating fuse-cells has a circuit for performing read/latch of data from a fuse-cell before the usual operation is started. The structure of a circuit system for performing read/latch data is shown in FIG. 1. Main signals or voltage waveforms are shown in FIG. 2. The structure and the operation of the foregoing circuit system will now be described.
Signal PONRST shown in FIG. 2 is a power-on resetting signal. The signal PONRST is made to be "L" level when the potential of external power supply Vdd is raised from 0V to power supply detection level VPONRST (2V or lower). Thus, supply of electric power can be detected.
Signal PONRST' is one of power-on reset signals. The difference from the signal PONRST will now be described. The signal PONRST is made to be "L" level when the external power supply Vdd is raised to the detection level VPONRST. On the other hand, the signal PONRST' is made to be "L" level after the external power supply Vdd is raised to a stable level (3V or lower). That is, the signal PONRST' is a signal indicating that the external power supply Vdd is raised to the stable level.
A voltage boosting circuit 201 shown in FIG. 1 is activated when the signal PONRST' is made to be the "L" level to boost the external power supply Vdd to boosted voltage VDDP having a predetermined level (6.5V or lower). The boosted voltage VDDP is supplied to a voltage converting circuit 202. The boosted voltage VDDP is converted into read voltage VDDR by the voltage converting circuit 202.
The voltage converting circuit 202 incorporates a VDDR regulator (not shown) for regulating the boosted voltage VDDP to the read voltage VDDR having a predetermined level (4.8V or lower); and a VDDR detector (not shown) for detecting whether or not the level of the read voltage VDDR is a predetermined level.
The VDDR regulator (not shown) uses reference voltage Vref to regulate the boosted voltage VDDP to the read voltage VDDR having a predetermined level.
The VDDR detector (not shown) uses the reference voltage Vref to output signal SVDDR for detecting whether or not the read voltage VDDR is raised to a predetermined level. The signal SVDDR is made to be "H" level when the read voltage VDDR is raised to the predetermined level. The signal SVDDR is supplied to a fuse-cell controlling circuit 203.
The fuse-cell controlling circuit 203 is activated when the signal PONRST' is made to be "L" level. When the signal SVDDR is made to be "H" level, the fuse-cell controlling circuit 203 executes a data read/latch sequence with respect to fuse-cells.
A fuse-cell circuit 204 incorporates a fuse-cell FC; a PMOS P202 serving as a load when data is read from the fuse-cell FC; an NMOS NI201 connected between the fuse-cell FC and the PMOS P202 and arranged to have a threshold voltage which is substantially 0V; a latch circuit for latching data read from the fuse-cell FC during the usual operation of the apparatus; and a connecting circuit TG for establishing the connection between the latch circuit LAT, the PMOS P202 and the NMOS NI201 and a node 241 during execution of the read/latch sequence.
The fuse-cell controlling circuit 203 makes signal FSREAD to be "H" level for a predetermined time when the signal SVDDR is made to be "H" level in a state in which the signal PONRST' is "L" level. The signal FSREAD is supplied to the PMOS P202 and the connecting circuit TG. During a period in which the signal FSREAD is "H" level, each of the PMOS P202 and the connecting circuit TG is brought to a conductive state.
Then, each of signal FSBIAS and signal FSWL is made to be "H" level for a predetermined time. As a result, the potential of the node 241 is changed depending on a fact whether the fuse-cell FC is "ON" or "OFF". The potential of the node 241 is supplied to the input terminal of the connecting circuit TG. The connecting circuit TG supplies an output which is the "H" level or the "L" level to the latch circuit LAT according to the potential of the node 241.
Thus, data stored in the fuse-cell FC is read before the apparatus is operated usually so as to be latched by the latch circuit LAT. The latch circuit LAT outputs latched data FUSE during the usual operation of the apparatus.
The reason why the foregoing fuse-cell controlling circuit 203 is arranged such that the voltage of the signal FSWL is the read voltage VDDR which is higher than the external power supply Vdd will now be described.
The power consumption of the semiconductor memory device has been reduced. At present, the level of the external power supply Vdd is lowered to 3V or lower. When the external power supply vdd is lowered to 3V or lower, the neutral threshold voltage (a state in which ultraviolet rays have been applied to cause electrons to be discharged from a floating gate, the state being hereinafter called a threshold voltage (initial state)) of the fuse-cell FC is sometimes higher than the external power supply Vdd.
In the foregoing case, when one of data items stored in the fuse-cell FC is the threshold voltage (initial state), the fuse-cell FC is undesirably turned off. Thus, correct data cannot be read.
To prevent the foregoing problem, the read voltage VDDR higher than the external power supply Vdd is applied to the gate of the fuse-cell FC. Thus, if the threshold voltage of the fuse-cell FC is the threshold voltage (initial state), the fuse-cell FC can correctly be turned on.
The foregoing read voltage VDDR can be obtained when the voltage converting circuit 202 converts the boosted voltage VDDP into the read voltage VDDR. To convert the boosted voltage VDDP into the read voltage VDDR, reference voltage Vref serving as a reference is required. Referring to FIG. 1, a circuit given reference numeral 205 is a reference-voltage generating circuit for generating the reference voltage Vref.
Hitherto, the reference-voltage generating circuit 205 is a band gap reference circuit which is free from considerable dependency on the power supply voltage and that on the temperature. The band gap reference circuit is operated to generate the reference voltage Vref. Thus, reference voltage Vref having a substantially constant level (1.25V or lower) can be generated regardless of change in the power supply voltage and the temperature.
As described above, the band gap reference circuit has an advantage that the dependency on the power supply voltage and that on the temperature can be reduced. However, if the reference voltage Vref generated by operating the band gap reference circuit is used to convert the boosted voltage VDDP into the read voltage VDDR, the converted read voltage VDDR undesirably has substantially a constant level regardless of change in the power supply voltage and change in the temperature.
On the other hand, the threshold voltage of the fuse-cell FC has dependency on the power supply voltage and that on the temperature. Therefore, if the external power supply Vdd has considerably been changed or if the apparatus is in a hot or cold atmosphere, there arises a problem in that the difference between the read voltage VDDR and the threshold voltage of the fuse-cell FC corresponding to stored data, that is, the margin, is undesirably reduced.